power integrity , Usb, Ethernet, Altium Designer, PDN analysis, Signal Integrity, Siemens HyperLynx 2D 3D, Ansys Siwave, Ansys HFSS, SI PI validation, PCIe Gen4, GMSL, FPD-Link, Electromagnetic behavior of high-speed designs, Board-level timing analysis, JEDEC-based memory interfaces, PCB stack-up optimization, LPDDR4, High-speed interface design simulation, MIPI CSI, Simulation methodologies, LPDDR5

altium , Orcad, Ansys AEDT, SiWave

Usb, Spi, DDR, Jtag, Pcie, Perl, Ethernet, Python, Uvm, UPF, systemverilog, Axi, SoC verification and validation, APB, I²C, Palladium Emulation, LPDDR, I3C, CPF, AHB

Git, Perl, Python, System Verilog, Tcl, Synopsys Design Compiler, primetime, Fusion Compiler, ICC2, Formality, LEC, UPF, Innovus, VHDL, EDA Tools, Linux Shell

Verilog, System Verilog, Nvme, Pcie, DDR, scoreboard assertions, functional coverage coding, Uvm, AHB, code coverage analysis, Axi, RTL debugging

Verilog, Jtag, CHI, Uvm, System Level Testing, Debugging functional and toggle coverage, systemverilog, DFT concepts, APB, Axi, lbist, MBIST

thermal management , python, perl, C, Silicon Validation, power management