hierarchical layout techniques, 3nm technology, Mentor Graphics Calibre, custom layout design, Totem tools, Cadence Innovus, device matching, Cadence XL, designing custom analog blocks, full-chip integration, IR drop analysis, low-parasitic layout practices

high-speed AMS circuits, analog and mixed-signal circuit design, signal integrity analysis, Circuit Simulation, lab equipment for testing and characterization, SerDes design, high-speed digital design

routing, floorplanning, Signal Integrity, CTS, Timing Closure, Placement, IR EM and variability analysis, low-power design, ASIC SOC physical design implementation, Physical Verification

Low-power Implementation, Physical Verification, Physical Design, Timing Closure, Floor Planning, EDA Tools, Power Grid Design, Power Planning

multidimensional designs, project management, Design Verification, layout of complex integrated circuits, component and system simulation, Vlsi Design, Problem Solving, architecture and logic design