ASICs, LPDDR, assertion-based verification, performance verification, Uvm, GLS low-power DV, formal verification, standard IP components, systemverilog, memory system architecture

System Verilog, Building test benches from scratch, ASIC verification using UVM

System Verilog, Tcp, Ethernet, Pcie, formal verification, Data path verification performance tests, Building test benches, RDMA, Zebu, HAPS, ASIC verification using UVM, Palladium, Veloce

Tcp, System Verilog, Ethernet, Pcie, formal verification, Forwarding logic Parsers P4, Building test benches from scratch, RDMA, Zebu, System Verilog constraints structures and classes, HAPS, ASIC verification using UVM, Verifying sophisticated blocks clusters and top level for ASIC, Palladium, Veloce

Tcp, Pcie, Ethernet, System Verilog, RDMA, Palladium, Test benches, Zebu, Veloce, ASIC verification using UVM, HAPS, Data path verification, formal verification