PCIe Formal Verification Engineer, PCI Express, formal verification, FPV, SVA, SystemVerilog Assertions, Questa Formal

Perl, Tcl Scripting, Python, System Verilog, Synopsys Mentor VIPs, PCIe Gen3, random constraint-based testing, verification methodologies, performance power optimization, SMMU, CXL 1.1, Coresight architecture, assertion-based verification, Uvm, UPF, CHI protocols, Axi, formal verification, power-aware verification, coverage-driven testing, SVA

Verilog, VHDL, formal verification, Chisel, JasperGold, VC Formal, Object-oriented Programming, systemverilog, Formal Abstraction Techniques

Perl, Verilog, Python, Tcl, SystemVerilog Assertions SVA, VHDL, Synopsys VC Formal, Cadence JasperGold, Property Specification Language PSL, systemverilog

Perl, Python, Tcl, PSL, OneSpin, JasperGold, VC Formal

Debugging, Scripting, formal verification, assertions, hardware micro-architecture, testplans

S3, Apis, Lambda, Docker, Terraform, FastAPI, Kubernetes, Python, AWS, observability and monitoring platforms, Langchain, CI CD, EKS, Autogen, LangGraph, A2A, Vector Databases, AI Agent frameworks, Pydantic, AI Technologies, prompt context engineering, MCPs, LLMs integration