Python, Jasper VC, Formal Questa, Formal 360-DV, Formal verification tools

formal verification, Synopsys VC Formal, Cadence JasperGold, systemverilog

Embedded Firmware, System Verilog, Digital Logic Design, Jtag, Verilog, Scripting Languages, DVFS, DCVS, IEEE1500, memory dump, MBIST, power management verification, micro-processor debug, UPF, scan dump, C Language, DFT architecture, reliability throttling

Verilog, Debugging, Automation Scripting, formal verification, AI-assisted Workflows, Protocol Verification, Property Checking, SVA, systemverilog, Equivalence Checking, Formal Analysis

Debugging, Scripting, formal verification, assertions, hardware micro-architecture, testplans

Shell, Python, Perl, formal verification technologies, complexity reduction techniques, high quality testplans, formal testbenches, root-causing counter-examples