Opengl, System Verilog, SV UVM based test benches, Vulkan API libraries, scripting languages such as Perl, Graphics architecture, HDLs like Verilog, debugging RTL TB issues using Verdi or similar tools, formal tools like Jasper or VC-Formal

Pli, Vcs, Verilog, regression management, Questa, Uvm, gate level simulations, NCSim, Modelsim, Testplan development, VHDL, SVA, dpi, formal verification methodology, assertions, functional coverage, verification planner

Spi, PYTHON, Uart, Usb, I2c, Ethernet, Pcie, PERL, Oop Concepts, LPDDR3, Ucie, DDR4, UCIe, Uvm, SV, AHB, CXL, D2D, C2C, NoC Interconnect verification, APB, Axi