Block level and Top-level physical implementation, Place and Route processes, Synthesis for high-speed designs, Physical Verification, Physical Design for complex Chiplets, Unix/Linux environment

Routing, Full-chip dependencies, FCFP, Defs, Feed planning, Timing Closure, Tile floorplanning, PhyV, Placement, FCT, Timing, Shapes, Pins, EM-IR

Routing, power analysis, Synthesis, EMIR, floorplanning, Placement, Physical Design Implementation, Power Planning

Block level and Top-level physical implementation, Place and Route processes, Physical Design, Synthesis for high-speed designs

Mentor-Calibre, Physical Verification, pegasus, Cadence Innovus, EM IR drop analysis, Static Dynamic IR analysis, EDA tool automation, Voltus

Routing, Python, Tcl, CTS, floorplanning, Placement Optimization, Antenna Density, LVS, Power Planning, IC Validator, Calibre, Physical Verification, Signoff Closure, Physical Design, ERC, Timing Closure, ECO Implementation, DRC