Unix, Linux, Perl, Tcl, Low power verification, floorplanning, Placement, power analysis, PNR implementation

C, Perl, Tcl, Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation

Physical Design Planning, Placement, Floor Planning

Verilog, System Verilog, python, Perl, Sta, Synthesis, Physical Verification, CTS, DFT tools, Extraction, Timing Analysis, Place And Route, Cadence, Synopsys

Clp, Sta, Timing Constraints, RTL synthesis, LEC, low-power design concepts

routing, Sta, CTS, ASIC PD methodologies, digital design fundamentals, Extraction, Floor Planning, PNR, Placement, EM IR closure, signoff