static timing analysis, Synthesis, verification methodologies, design optimization techniques, low-power design methodologies, Power Planning, Place And Route, FC Innovus, Clock Tree Synthesis

C, Routing, Perl, Tcl, Clock Planning, primetime, floorplanning, ICC2, LEC, Calibre, Innovus, Physical Verification, Placement, Timing Closure, Physical Design Implementation, EDA Tools

Python, Tcl, floorplanning, Physical design flows, Logical Equivalence, Clock CTS, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route

hardware engineering , automation, physical design methodologies, lower technology nodes, power gating, sign-off optimizations, multi-voltage domains, deep sub-micron technology, Netlist2GDS, ASIC design flows, Floorplan, Circuit Design, device physics

redhawk , Tcl, Perl, Python, SDC, Foundry PDKs, Implementation tool suite, EDA Tools, Power gating, Cadence, primetime, Tempus, Synopsys ICC2, CPF, Timing Analysis, TSMC, Physical Design, Synopsys, UPF, Cadence Innovus, Sta, Multi-voltage domains, Voltus, Signoff tools, Samsung, Low-power design techniques

Debugging, Perl scripting, Cadence Tools, IP QA, Mentor Calibre, CMOS circuit design fundamentals, Innovus, RTL2GDS, CMOS layouts, Apache RedHawk, Genus, Synopsys Prime Time

routing, Shell scripting, Static Timing Analysis, Python, Perl, Ddr3, Tcl, Sta, IR drop, OCV, CTS, LVS, LPDDR PHY hardening, ECO implementation, antenna checks, MMMC, POCV, floorplanning, EM analysis, CRPR, Physical Verification, Signal Integrity, crosstalk, DRC, Timing Closure, Placement, ASIC Physical Design flow, DDR5, DDR4, AOCV

clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, Power Mesh, PNR Floor Plan, Timing Signoff