Verilog, Ethernet Protocols, LINT, Rtl Design, spyglass, Synthesis, cdc, RDC, PPA optimization, systemverilog

Python Scripting, Git, PrimeTime or equivalent tools, Modern SOC tools including Spyglass, Version control systems such as Perforce, ASIC design flow, Low power digital design and analysis, Digital Design, C embedded experience, VCS simulation, Cadence Conformal, ICManage, ASIC design in sub-20nm technology nodes, Questa CDC, RTL design in Verilog, Circuit timing STA

Automation Frameworks, Sta, LINT, Memory operation, Synchronous design concepts, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, spyglass, Synthesis, device physics, CDC methodologies