Java, C, Python, SIMD vectorization, Cache-aware execution, Performance profiling, Parallel execution strategies, qemu, Benchmarking, Optimization

Arm, Python, RTL simulation, Debug, functional coverage closure, RISC-V, regression automation, x86 architecture, Uvm, SVA, systemverilog

C, Verilog, automation, Scripting, coverage closure, RTL testbench debugging, Uvm, systemverilog