debugging and root-cause analysis, quality engineering best practices, Reliability Testing, test automation infrastructure, test automation using Python, end-to-end test strategies

C, Perl, Python, System Verilog, formal verification tools, Microarchitecture, SOC integration, Uvm

static timing analysis, Perl, Python, Tcl, multi-clock domain designs, constraint development, STA tools, clock gating, Cadence synthesis tools, Timing Analysis, CPF-based power intent, multi-voltage domains, UPF, ECO flows, timing convergence, RTL-to-gate synthesis, Timing Closure, low-power design techniques, constraint validation

Dynamodb, Vue.JS, Lambda, RDBMS, Cloudwatch, Docker, Terraform, ECS, Flask, Dynatrace, Splunk, FastAPI, Python, AWS, Api Gateway, Harness, GitHub Actions, Fargate, Next.js

Cadence - Virtuoso, Tcl, Python, Perl, Spice Simulator, Synopsys, Uvm, SV, Mentor tools, Verilog-A, Verilog-D, Cadence, Verilog Hdl, Verilog-AMS, AMS simulation environment

Sql, Uat, Sit, Data Warehousing, Etl Testing, Python, Data Migration, Automation Frameworks, load validation techniques, mock loads, cutover plans, data lake architectures, structured project frameworks, data validation processes, data quality cleansing strategies

Ml, Scripting, Python, Tcl, Skill, Power Distribution, crosstalk mitigation, Ai, LVS, Physical Verification, LPDDR PHY blocks, Signal Integrity, simulation correlation, high-speed layout design, impedance matching, DRC, Parasitic Extraction

distributed storage , Algorithms, Java, C, File System, Python, ML infrastructure frameworks