arm architecture , C, Soc Architecture, Embedded Software, Verilog, Firmware, CPU architecture, scripting in Python, Emulation, Simulation, AMBA protocols, systemverilog, Assembly

Verilog, Sata, Python, Perl, Usb, DV methodologies, Uvm, constrained random verification, functional coverage, PCI Express, VMM, systemverilog

Python, Scipy, Pytest, Git, Numpy, AI coding assistants, unittest

Xpath, C++, Gcc, Xslt, Sql, Git, Linux, Xml, Javascript, System Verilog, Python, Assembly languages, SGE or other DRMS, Uvm, HTML DOM, LLVM, SVA

Ovm, Perl scripting, Verilog, Post-silicon bring-up HW-SW debug, AXI protocol, DDR PHY architecture, Uvm, JEDEC standards, systemverilog, DFI protocol, LPDDR4, debug and root-cause skills, SS SoC post-silicon issues, AHB, LPDDR5