DFT insertion flows, JTAG 1149.1, IEEE1687, IEEE1500, Cadence tools and flows, SoC ASIC Digital Design, Timing Analysis, Verification of ATPG testbenches, Debug and Analysis of failures, LBIST, scan chain insertion, compression scan insertion, equivalency checks

Python, Tcl, Product test engineering practices, Manufacturing test flows, Fault modeling and coverage analysis, Scan insertion and optimization, DFT methodologies, ATE environments, ATPG development, Silicon bring-up, SoC DFT architecture