hierarchical layout techniques, 3nm technology, Mentor Graphics Calibre, custom layout design, Totem tools, Cadence Innovus, device matching, Cadence XL, designing custom analog blocks, full-chip integration, IR drop analysis, low-parasitic layout practices

C, Perl, Unix Scripting, Quality Assurance, Python, SPICE Circuit Simulators, Circuit Design, MOSFET Electrical Behavior, Standard Cell Layout Design, Transistor-Level Device Physics, Characterization Modeling, Standard Cell EDA Views, PPA Performance, EDA Tools

cadence spectre , Python, Analog Mixed Signal Verification, Skill, Xcelium, SystemVerilog-RNM, Uvm, Model vs Schematic Comparison, High-speed Design AMS Verification, Behavioral Modelling, Synopsys VCS FineSim, Verilog-AMS, AMS Designer, Synopsys AMS tools, Cadence Virtuoso, Mixed Signal Modelling, SerDes Verification

Perl, Python, Tcl, Skill, Calibre PVS, Cadence Virtuoso, High-voltage process technologies, IR drop, Physical verification tools, PEX, Reliability-aware layout, Antenna density, High-current routing, Layout methodology improvements, LVS, Parasitic control, Latch-up prevention, Electromigration, Noise isolation, Thermal effects, ERC, DRC, Extraction and reliability tools, Tape-out readiness, Guard rings

Layout optimization, Samsung Foundry process technologies, ERC, PEX closure, LVS, Analog Layout Design, Custom analog layout DRC, FinFET technology

AI automation in layout, I/O Library and Analog Mixed-signal IP development and verification, Cadence Virtuoso Layout suite, Siemens CALIBRE verification tools, Planar and FinFET layouts, Script Programming, SKILL Programming