Samsung Foundry process technologies, layout optimization, ERC, PEX closure, LVS, Analog Layout Design, custom analog layout DRC, FinFET technology

caliber , Mentor Graphics, Cadence Virtuoso

layout verification , Ant, PERC, LPE, AI automation in layout, LEF generation, Cadence Virtuoso Layout suite, Siemens CALIBRE verification tools, SKILL Programming, EM, Analog Mixed-signal IP development, Ir, LVS, Dfm, PNR, Physical Design flow, ERC, DRC, Script Programming, FinFET layouts

Electrical check, Scripting and automation, IP integration, Custom layout design, Physical verifications, LVS, Analog layout techniques, Ageing and Reliability Compliance, Data converters, Floorplan constraints, Analog Macros, power management, DRC, Full Spectrum Verifications, High-speed Analog Serdes, Pll, High-speed IPs

Custom layout design, High-speed IPs, Floorplan constraints, High-speed Analog Serdes, Data converters, LVS, Scripting and automation, Analog Macros, IP integration, Pll, Physical verifications, Analog layout techniques, power management, DRC, Ageing and Reliability Compliance, Full Spectrum Verifications, Electrical check

Cadence PVS, Mentor Calibre, tape-out, analog block integration, CMOS Circuits, BiCMOS circuits, Layout Design, Cadence Virtuoso, chip level integration verifications, debugging DRC

Python, Tcl, timing sign-off, PDV, Physical Design, place-and-route analysis, Cadence Innovus, Siemens Mentor Calibre, advanced technology nodes 5nm or lower

Cadence Tools, FinFET process technologies, DRC LVS checking flows with Calibre