Integrated circuits, Design Rule Checks, Analog Layout Design

shielding , Tcl Scripting, Perl, Layout dependent effects, Signal shielding, Semiconductor device physics, Cadence Virtuoso XL VXL, Latchup, Skill, Parasitic noise, Calibre, EMIR, Noise isolation, Esd, Supply consideration, Isolation, Well’s substrates, Layout matching, Double patterning, Device matching

Samsung Foundry process technologies, layout optimization, ERC, PEX closure, LVS, Analog Layout Design, custom analog layout DRC, FinFET technology

caliber , Mentor Graphics, Cadence Virtuoso

layout verification , Ant, PERC, LPE, AI automation in layout, LEF generation, Cadence Virtuoso Layout suite, Siemens CALIBRE verification tools, SKILL Programming, EM, Analog Mixed-signal IP development, Ir, LVS, Dfm, PNR, Physical Design flow, ERC, DRC, Script Programming, FinFET layouts

Automated PnR, High-speed SERDES IO PHY Layout design, Signal integrity issues, Analog IO design principles, CMOS and FinFET technologies, Block PnR

CMOS Circuits, Mentor Calibre, Cadence PVS, LVS, tape-out, layout editing tools, productivity-enhancing tools, chip-level floorplanning, ERC, chip-level integration verification, DRC, design scripts, Cadence Virtuoso, BiCMOS circuits, analog block integration

Electrical check, Scripting and automation, IP integration, Custom layout design, Physical verifications, LVS, Analog layout techniques, Ageing and Reliability Compliance, Data converters, Floorplan constraints, Analog Macros, power management, DRC, Full Spectrum Verifications, High-speed Analog Serdes, Pll, High-speed IPs