Clarity, MIPI D-PHY, Cadence Sigrity, PCIe Gen5, TDR, 10 Gigabit Ethernet, USB 3.x, VNA, SIwave, Keysight ADS, MIPI CSI, Ansys HFSS, high-bandwidth oscilloscopes, C-PHY, LPDDR memory channels

Pcie, Verilog, Ethernet, Synthesis, cdc, UALink, Simulation, timing considerations, UCIe, systemverilog, LINT, CXL

power integrity , Perl, Python, Tcl, Sta, primetime, Cadence Innovus, Tempus, EM IR analysis, Voltus

conformal lec , Clp, Perl, Python, Tcl, Fusion Compiler, Formality, LEC, MCMM methodologies, UPF, Cadence Genus, Synthesis, Synopsys Design Compiler, RTL-to-GDS, CPF, Low Power Verification

UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), C, C++, Shell, Pcie, Perl, Arm, Python, Tcl, Systemc, MCU, Hardware Emulation Platforms, RISC-V, UCIe, systemverilog, Verification Methodology, AMBA, Axi, Formal Model Equivalence Checking Tools, formal verification, VC Formal

clocking , Verilog, EDA tools for synthesis, LINT, Use of AI for design, cdc, SoC-level design and integration, Synthesis flows, Rtl Design, spyglass, VHDL, Verification methodologies, RDC, Digital design principles, Resets, Timing Constraints, Micro-architecture design, Low-power design techniques, Timing Analysis

Perl, Python, Tcl, Xcelium simulation, vManager, Real-Number Modeling, Verilog-AMS, JasperGold, Uvm, SVA, systemverilog