Static Timing Analysis, Advanced PHY technologies, Data movement and interconnect fabrics, Design Verification, Network-on-Chip NoC architectures, SoC architecture integration, Complex multi-die or chiplet-based architectures, High-bandwidth and low-latency interconnect technologies, High-bandwidth memory-centric systems, Dft, Analog front-end AFE subsystems, High-speed SerDes interfaces, Physical Design, Packaging technologies, Low-Power Design Methodologies, Silicon Bring-up and Productization, Signal integrity considerations, Mixed-signal IPs, Rtl Design

LINT, chip design flow, cdc, Memory BIST, verification processes, Synthesis design for testing, UPF, Physical Design, RDC, ATPG, ASIC design methodologies, chip architecture design methodologies, Low Power Optimization Estimation