static timing analysis, Synthesis, RISC CPU IP, ARM CPUs, Emulation, chip validation, Timing Analysis, CPU microarchitecture, SoC design methodology, Physical Design, IP integration, CDC analysis, Rtl Design, Floor Planning, linting, BUS Protocols, Timing Closure, characterisation, silicon bring-up, Verification, equivalence checking

react.js , Apis, Azure Data Bricks, Data Modelling, Microservices, HTML, Data Quality, Typescript, Distributed Systems, Rest Apis, Python, LLMs, RAG systems, workflow orchestration, vector databases, agent frameworks, Analytics, AI integration, data ingestion, backend services, ETL pipelines

Verilog, Integration, System Verilog, ATB-AMBA protocol, SoC development, Uvm, Debug architecture, Gate Level simulations, verification testbench, Axi, ASIC Design, Power aware simulations, Verification, Validation, AHB

Python, FineSim, Synopsys VCS, Skill, Xcelium, Verilog-AMS, SystemVerilog-RNM, Cadence Virtuoso, Spectre

System-level SI simulation, 3D Modeling, S-parameter extraction, Linux environments, Ansys SIwave, Allegro SIP, EDA Tools, Circuit simulations, IBIS model development, agilent ads, Cadence PowerSI, Signal integrity analysis, Siemens Advanced Solvers

Java, Scala, Distributed Systems, Python, Go, Backend Systems Infrastructure