bist , Perl, Debugging, Python, Tcl, Logic Design, Sta, RTL, Scan, make, tessent, on-chip scan compression, gate level simulation, Fault Models, automation methods, ATPG, pattern generation, VLSI simulation tools, Fault Simulation

layout verification , System Verilog, Computer Engineering, clock voltage domain crossing design, ASIC Design, Electrical Engineering, Computer Science, design rules, low power designs