Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, AMBA, Test Bench, transaction level modeling, AXI4

C, Pcie, Perl, Python, Tcl, UFS, HSIO PHY Controllers, Skill, Open Verification Methodology, USB2, systemverilog, MIPI, USB3, Universal Verification Methodology

Embedded C, Can, Jenkins, Jtag, Python, Cadence Palladium, SWD, AUTOSAR MCAL, MISRA C, CAN XL, CAN-FD, ISO 26262, Synopsys ZeBu, ARM Cortex-M

Devops, Git, Terraform, Docker, Perl, Arm, Azure, Kubernetes, Python, Tcl, AKS, Bicep

Python, Scripting Languages, Silicon Validation, lab instruments, FPGA Emulator, NVLink, Troubleshooting, BERT, PCI Express, functional validation, HSIO validation, Post-Si bring-up, DSOs, CXL, tuning of HSIO interfaces, Protocol Logic analyzers

congestion management , Software debugging, Python, Load-balancing technologies, Network Operating Systems, Switching platforms, Linux-based systems, Traffic Management, Layer 2 and Layer 3 networking technologies, Networking ASICs, Performance Analysis, SDKs, Network infrastructure software

Usb, Fpga, Perl, Pcie, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, test bench infrastructure, transaction level modeling, AXI4

Verilog, System Verilog, AI-powered tools, Timing Closure, EDA design processes, ASIC Design, Simulation and debugging, Functional verification tools, Synthesis tools