DFT verification, MBIST, debugging GLS, Analog IPs, Scan, ASIC SoC designs, DFT EDA tools, IEEE1149, DFT validation, HSIOs, Dft, timing generating test cases, CTL generation, 1500, 1687

bist , Perl, Debugging, Python, Tcl, Logic Design, Sta, RTL, Scan, make, tessent, on-chip scan compression, gate level simulation, Fault Models, automation methods, ATPG, pattern generation, VLSI simulation tools, Fault Simulation

Gerrit, Artifactory, Git, Jtag, Python, CloudBees, debug architecture, MBIST, CoreSight, Dft, trace scan, SoC debug ecosystems, ELA telemetry frameworks, on-chip debug architectures, IJTAG

Pcie, Perl, Debugging, Ethernet, Python, Emulation, Simulation, Uvm, systemverilog, RTL Verilog, high-speed protocols, SVA

Github, Jenkins, Pytest, Git, C, Verilog, System Verilog, Python, Git actions

C, Pcie, Perl, Ethernet, Ruby, Python, TDR, Oscilloscopes, IO electrical validation, protocol logic analyzers, VNA, Memory and HSIO interfaces, SI PI validation, DDR5, Post-Si IO electrical interfaces, LPDDR5

Usb, Fpga, Soc Architecture, Pcie, Perl, Debugging, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, AMBA, formal verification, Test Bench, transaction level modeling, AXI4