rtl verification , simvision , Gen5., Pcie, PCI Express, Design Verification, design verification testing, DV, systemverilog, Uvm, SVA, TLP, DLLP, LTSSM, Verification IP, vip, Functional Coverage, Assertions, Axi, Vlsi, Semiconductor, Verdi, DVE, Gen3, Gen4

Fpga, Perl, Python, object-oriented programming, RTL, test plan development, Uvm, emulation platforms, systemverilog, automation scripts

Ovm, DDR, Pcie, Perl, Verilog, Ethernet, Python, System Verilog, Tcl, UCIE, Uvm, CXL

Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, Post-silicon debugging, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming

Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA

performance verification of ASICs, assertion-based verification, Uvm, formal tools, ASIC standard interfaces, systemverilog, Design Verification, memory system architecture, verification components

Ovm, Spi, Shell, Pcie, Verilog, I2c, Python, Usb, Can, Perl, Ethernet, Tcl, ARM Protocols, IP Verification, Uvm, GLS, Mipi, Emulation, Test bench model VIP development, dsi, LPDDR, CSI, SoC Verification, SV, AMs, LEC, Functional coverage, Axi, APB, AHB

System Verilog, Building test benches from scratch, ASIC verification using UVM