About Texas Instruments

At TI, we design and manufacture analog and embedded semiconductors trusted in the world's most critical systems. Our Physical Design team is the execution engine behind every chip TI ships — transforming design intent into silicon reality with precision, quality, and speed. Now, we're raising the bar.

About the Role

We are seeking a Principal Physical Design Engineer to join our elite CFET group as a Subject Matter Expert (SME) with a TI-wide charter. You will own the complete Digital Backend flow from RTL to GDSII, drive execution excellence across EDA, Library, Memory, and IP teams, and represent TI with authority in customer engagements.

This role sits at the intersection of deep technical expertise, cross-functional leadership, and customer advocacy — making you a force multiplier whose impact resonates far beyond any single project.

What You'll Do

Methodology & Standards Ownership

Define and establish Physical Design methodologies, flows, and best practices with a TI-wide charter — setting the quality benchmark every TI project measures itself against
Evaluate and qualify new EDA tools, methodologies, and process nodes — driving adoption decisions with data-driven recommendations
Shape designs upstream — embedding design-for-implementation thinking into architecture and front-end decisions before they become costly backend constraints

Sign-Off Authority & Quality Guardianship

Own sign-off on the complete Digital Backend flow from RTL to GDSII across concurrent projects
Full accountability for floorplanning, placement, CTS, routing, STA, EM, IR, and physical verification
Stand as TI's physical design quality authority — your approval the final assurance before any product advances to tape-out

Cross-Functional & Customer Engagement

Serve as TI's primary technical representative in customer engagements, design reviews, and partner discussions — communicating complex physical design decisions with authority and clarity
Orchestrate collaboration with EDA, Library, Memory, and IP teams — eliminating flow bottlenecks and aligning execution priorities
Raise the implementation bar across every TI project through active cross-team engagement

Mentorship & Community Building

Elevate the physical design community at TI — mentoring engineers, standardizing implementation practices, and building institutional knowledge that outlasts any individual tape-out
Own the strategic direction of physical design at TI — your methodology decisions and quality standards becoming the foundation for TI's next generation of products

What You Bring

Experience: 12+ years of hands-on Physical Design / Digital Backend implementation experience

Education: B.S. or M.S. in Electronics Engineering, Electrical Engineering, or VLSI Design

RTL-to-GDSII Mastery: Proven expertise in end-to-end flows using Synopsys and/or Cadence toolchain

Independent Ownership: Demonstrated ability to own and deliver complex designs from specification through sign-off

Deep Backend Knowledge: Expert-level understanding of timing closure, power integrity, signal integrity, and physical verification (DRC/LVS/ERC)

Process Node Expertise: Strong understanding of process node design rules and implementation constraints

Library & IP Collaboration: Experience working with or alongside Library, Memory, and IP teams in a product development context

Communication: Strong written and verbal skills with experience presenting to internal stakeholders and external customers

Bonus Points If You Have

12–18 years of progressive physical design experience with increasing ownership and scope

Hands-on experience with mixed-signal designs — analog-digital co-design, guard-ring strategies, substrate coupling mitigation, and mixed-signal floorplanning

Prior experience as an SME, methodology lead, or technical architect — having defined implementation standards that others adopted and built upon

Proficiency in EDA flow development and scripting — Tcl, Python, or Perl for custom flow automation

Experience in customer-facing roles — design reviews, technology presentations, or pre-silicon collaboration with external customers

Knowledge of DFT integration within the physical design flow — scan insertion, BIST, and boundary scan

Exposure to power management architectures and low-power implementation — multi-Vt, power gating, and voltage islands

Why TI

Set physical design standards that shape TI's next generation of products
Work with cutting-edge EDA tools across advanced process nodes
Be the technical authority whose implementation decisions protect every TI chip that reaches the market
Competitive compensation, comprehensive benefits, and a platform to build your technical legacy at scale

Principal Physical Design Engineer Digital Backend (RTL to GDSII)