automation, Scripting, environment development, mixed signal verification fundamentals, Real model creation, verification planning, behavioral modelling of analog blocks, SoCs, model validation, verification of Power management IPs, PSL SV assertions development, Verilog-AMS, SV Verilog, VerilogA

System Verilog, Visual Studio Code, Uvm, Spectre, Cadence Xcelium-AMS, Hspice, Mixed-Signal verification, GitHub Copilot

Python, SystemVerilog RNM, Analog Mixed-Signal circuits, Verilog-A, EDA Tools, Cadence

Verilog, Uvm, testbench creation, code coverage analysis, DFI protocols, logic simulation, systemverilog, Verilog-A, score boarding, AMS simulations, RTL debugging