Regression Analysis, Verilog, Python, scripting for simulation automation, silicon-debug exposure, XA simulation, post-layout verification, custom analog circuit design, result extraction, mixed-signal design, mixed-signal validation methodologies, waveform processing, waveform debug, memory peripheral circuit design, transistor-level circuit design, CMOS device operation, circuit build entry, AI-enabled engineering solutions

litmus , Tcl, Python, Innovus, Cadence EDA tools, Tempus, Certus, Conformal, Voltus, AI tools, pegasus, Genus

C, Vcs, Jtag, Perl, Verilog, Python, Tcl, Debug features, UPF support, Low Power features, systemverilog, Scan Boundary Scan, VHDL, DFX Design Planning

C, Vcs, Jtag, Perl, Verilog, Python, Tcl, UPF support, systemverilog, Scan Boundary Scan, VHDL, DFX Design Planning, Low Power technologies

litmus , Tcl, Python, Genus, Tempus, Cadence EDA tools, Certus, Conformal, AI tools, Voltus, pegasus, Innovus

Routing, Python Scripting, Tcl Scripting, primetime, floorplanning, Tempus, Cadence Innovus, Calibre, Physical Verification, Physical Design, Timing Closure, Placement, ECO Implementation, ICV, Synopsys ICC2

Verilog, Soc, Timing Closure, IP integration, Synthesis, linting, systemverilog, ASIC, Digital Design, gate-level simulations