Ml, Python, Tcl, Sta, Synthesis, power-state tables, power-gating, Fusion Compiler, low-power flows, Ai, Physical Verification, isolation, Innovus, PNR flows, FM VSI, level-shifter, voltage areas, UPF concepts, electrical checks

C, Vcs, Jtag, Perl, Verilog, Python, Tcl, Debug features, UPF support, systemverilog, Scan Boundary Scan, VHDL, DFX Design Planning, Low Power technologies

Routing, Automation, HBM3, Design validation, Parasitic modeling, Placement, Tape-out revisions, Industry standard simulators, DDR5, Floor-planning, Memory Logic Analog circuits, Modeling and simulation, LPDDR6, LPDDR5

Electronic Design Automation (EDA Tools, Static Timing Analysis (STA, Verilog, Scripting, Digital Circuit Design, systemverilog