power optimization , Perl Scripting, PPA trade-off decisions, CTS, High frequency data-path intensive Cores, Advanced STA concepts, Block level PnR convergence, PD implementation, Cadence Innovus, LVS, Physical Implementation, Timing convergence, Physical Verification, Timing Closure, DRC, PDN, Timing convergence in PTSI Tempus, Floor-planning, Place And Route, Synopsys ICC2, formal verification, Clocking architecture

static timing analysis, Python, Asic Physical Design, place-and-route Encounter Innovus ICC, high-speed SerDes, physical verification DRC LVS, 3DIC implementation methodologies, DFT methodologies, Verilog RTL, Cadence Virtuoso, Genus Design Compiler, RTL Compiler, Clock Tree Synthesis, scripting or programming languages, ASIC synthesis

Routing, Physical Design Methodologies, Tcl tool scripting, RTL-to-GDSII implementation, DDR design knowledge, primetime, Placement, Calibre, Genus, Innovus, floorplanning, MultiTap-CTS