System Architecture, C, Perl, Ruby, Python, Board platform-level debugging, Debug techniques and methodologies, Technical debug and validation strategy

Usb, C, C++, Debugging, Test Plan, Object Oriented Programming, Writing Test Cases, Oop, DDR, Ethernet, Pcie, Perl, Tcl, Function coverage, Coverage driven verification, Uvm, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, CXL, Test bench development, Simulation, System-Verilog

Networking Concepts, C, Ethernet, Python, test automation, digital hardware, laboratory measurement techniques, hardware software integration, FPGA prototypes, Data Analysis, Embedded Systems, ASICs

Clp, perl, Tcl, python, power gating, UPF, DVFS, LEC, Cadence Genus, Fusion Compiler, Innovus, primetime, Synopsys ICC2, Tempus, CPF, Tk

System Architecture, C, Perl, Ruby, Python, Board platform-level debugging, Debug techniques and methodologies, Technical debug and validation strategy

Routing, Python, Tcl, CTS, floorplanning, Placement Optimization, Antenna Density, LVS, Power Planning, IC Validator, Calibre, Physical Verification, Signoff Closure, Physical Design, ERC, Timing Closure, ECO Implementation, DRC

Tcl, PERL, Cadence, Floor Planning, SI Aware Routing, Synopsys, Voltage Islands, Timing Analysis Closure, ECO Tasks, Physical Verification, Timing Optimization, Substrate-bias Techniques, Asic Physical Design, Power Gating, Physical Design, Timing Closure on High Speed Interfaces, low power design, IR Drop Analysis, Antenna Checks, Signal Integrity Closure