Perl Scripting, Tcl, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, IC design, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, High Frequency Design, Power Gating, PDN Methodology, PPA Targets, Timing Signoff

Synopsys Formality, Cadence Conformal, ASIC Design Flow, Synopsys Design Compiler DC DCG, SDC timing constraints, UPF CPF, Logic Equivalence Checking LEC, Cadence Genus

power analysis, 3D IC design, Physical Design flow, IR Signoff Tools, Ansys tools, PTPX, Low power implementation techniques