Scripting Languages, Perl, Tcl, Physical Verification sign-off flows and tools, PDK concepts, Physical Design implementation flow, Fusion Compiler, Foundry PDKs, ICC2, SVRF rule decks, Calibre, Innovus, ICV, Design Rules, Mixed-signal SOC environments, Backend design methodologies, Tech LEF, Custom IC design flows, Layouts, ESD reliability analysis, PERC methodologies

conformal lec , Perl, Shell script, Tcl, DFT Insertion, Fusion Compiler, Conformal Low Power, Formality, VCLP tool, Tempus, primetime, Logic equivalence check, UPF Low power concepts, Physical Synthesis, Genus, pre-STA timing analysis, functional ECO flow

low power design, Timing Closure, Synthesis, Verilog RTL development, Front-end EDA tools, RTL design verification, Digital IP ASIC design, Post silicon validation, Design quality checks

synopsys primetime , Synopsys FusionCompiler, Advanced Node Experience, Timing Signoff Tools, Physical Design Flow, SDC Proficiency, Advanced Clocking

conformal lec , Clp, Perl, Python, Tcl, Fusion Compiler, Formality, LEC, MCMM methodologies, UPF, Cadence Genus, Synthesis, Synopsys Design Compiler, RTL-to-GDS, CPF, Low Power Verification