ESD protection methodology, mixed-signal system modeling, analog mixed-signal IC design, custom IC layout, systemverilog, customer application support, lab validation

Jasper, Perl, Verilog, Debugging, Python, Tcl, Xcelium, Memory Test methodologies, Modus, Scan Insertion, VHDL, ATPG, Genus, silicon bring-up

JTAG TAP, Scan Compression, BISR, MBIST, CPF, TestMAX, UPF

boundary scan , Perl, System Verilog, Python, Tcl, scan architecture, MBIST, DVE Verdi, JTAG protocol, Uvm

Spi, Verilog, I2c, System Verilog, Scan Insertion, Digital DFT design, Logicbist, Mentor, Cadence, TetraMax, Gate level simulations, Synthesis, AMBA, ATPG, Digital RTL coding, Timing Constraints, Synopsys, PMIC

DFT architecture, coverage analysis, Memory-BIST, ATPG pattern generation, compression at core level, Scan Insertion, SSN architecture, clock architecture, timing simulations, no-timing simulations, occ