random testing , Perl, Python, SV, coverage metrics, Profiling Tools, Uvm, X prop, functional coverage

Computer Architecture, Perl, System Verilog, Python, Network on Chip verification, Configurable IP verification, VIP integration, Bridge checkers, Coherent Protocols CHI, Protocol checkers, AMBA protocols

Perl, Python, Tcl, Calibre, ANT Density, Physical Verification, Mentor Calibre, ERC, DRC, LVS, Dfm

AI ML Accelerators, functional coverage, systemverilog, SVA, vector processing units

Jasper, Perl, Python, Asic verification, verification methodologies, Synopsys Magellan, Uvm, systemverilog, Cadence IEV, VC Formal, functional coverage, SVA

Debugging, System Verilog, Axi, Problem-solving skills, CHI, ARM bus protocols, APB, SoC system architecture, Uvm, AHB, Virtual Memory concepts

static timing analysis, Digital Logic Design, Perl, Verilog, Python, Scripting, Tcl, Synthesis, memory subsystems, cdc, SOC design, Uvm, IP integration, systemverilog, Rtl Design, Axi, formal verification, EDA tool flows, LINT, Verification, bus architectures, automation of design flows