simulator , compiler , C, Verilog, Arm, Python, System Verilog, Embedded C Verification, Assembler, Floating point instructions implementation verification, RISC-V, Uvm, Logic Verification, processor toolchains, functional processor simulators

Perl scripting, C, Verilog, Python, Axi, Uvm, AHB, systemverilog

Perl, Bash, Python, Tcl, C, shell scripting, simulation and emulation environments, verification methodologies, Linux Unix environment, SystemVerilog UVM, test plan creation and execution

C, C++, Perl, Verilog, Xml, Python, Tcl, Silicon process technologies, Regression management, UVM methodology, Cadence, systemverilog, Assertions, Coverage-driven verification, Constrained-random testing, Formal debug, VHDL, Verification simulation, SoC verification environments, Synopsys, formal verification

C Programming, System Verilog, DSP Image RADAR processing, SOC Chip level Cluster Sub-System Verification, Interconnect NIC FlexNoC Cache Coherency, Uvm, Microcontroller and Microprocessor architecture, ARM Cores

Scripting Languages, Perl, Tcl, Physical Verification sign-off flows and tools, PDK concepts, Physical Design implementation flow, Fusion Compiler, Foundry PDKs, ICC2, SVRF rule decks, Calibre, Innovus, ICV, Design Rules, Mixed-signal SOC environments, Backend design methodologies, Tech LEF, Custom IC design flows, Layouts, ESD reliability analysis, PERC methodologies

Shell, Perl, Scripting, Tcl, debug methodologies, automation using Python, Uvm, assertion-based verification, systemverilog, regression frameworks, coverage closure, formal verification, Functional Verification

Python, FineSim, Synopsys VCS, Skill, Xcelium, Verilog-AMS, SystemVerilog-RNM, Cadence Virtuoso, Spectre