additive manufacturing , Ml, IIOT, Enovia, 3D CAD, Plm, Cloud, ASME Y14.5 Geometric Dimensioning and Tolerance Standards, 3DX, Ai, Nx, Fabrication processes, Model-Based Engineering, Manufacturing methods, Catia, Electromechanical packaging, Teamcenter, Creo, Engineering design tools

Verilog, Routing, Physical Design, VHDL, Placement, Floor Planning, Physical Verification, Clock Tree Synthesis, RTL to GDS flows

static timing analysis, low-power design methodologies, micro-architecture development, Cadence-based ASIC design environments, LINT, SystemVerilog RTL design, formal verification, Dft, cdc, Logic Synthesis

static timing analysis, Logic Synthesis, Cadence-based ASIC design environments, micro-architecture development, SystemVerilog RTL design, Lint CDC formal verification, low-power design methodologies and flows