Full Scan Compression, JTAG Boundary Scan, ATPG pattern generation, Scan chains, Fault Simulation

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools

logic bist , Makefile, Windows, Perl, Linux, Verilog, Ruby, System Verilog, DFT verification, Memory BIST, UVM testbenches, Scan ATPG

boundary scan , Verilog, Python, Cadence Tools, ATPG, MBIST, Synopsys

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, UVM based verification frameworks, TLM

Perl, Python, JTAG IO BIST, Memory BIST, SV, ATPG, Uvm

boundary scan , Test Engineering, static timing analysis, Soc Architecture, Functional Testing, Test Execution, Testing, coverage analysis, lab equipment, debugging failures, Scan Insertion, EDA flows, MBIST, Cadence, Digital Design, Tessent, RTL synthesis, silicon bring-up, test architectures, test patterns, pattern generation, LBIST, Synopsys, ATPG tools