Verilog, Rtl Design, RTL Coding, Micro-architecture, systemverilog, RTL Design Engineer

Pytorch, Python, Hugging Face, ESPnet, Model training, ASR fine-tuning, nemo, Evaluation frameworks, MLflow logging

Logic Design, Verilog, Microprocessors, low power design, LINT, cdc, Design Compiler, Memory controller designs, AMBA protocols, ASIC RTL Design, primetime, Synthesis, Axi, Asynchronous interface, APB, timing concepts for ASIC, RTL Coding, micro-architecture, Multi Clock designs, AHB, System-Verilog

Verilog, System Verilog, Sta, CDC tests, CPU ARM, RISC-V, backend tools, timing constraint files, low power design, Synthesis, Dft, VHDL, Pd, RTL Coding, Lint checks

Perl, Shell scripting, Python, Sta, SDC constraints, RTL design using Verilog, ASIC SoC development, Timing Analysis, systemverilog, digital design concepts, VHDL, Functional Verification, RTL debugging, UVM-based verification environments, Timing Closure, synthesis flows

Tensorflow, Pytorch, Python, MLops, machine learning engineering, generative AI, Ai Development

redhawk , Tcl Scripting, Python Scripting, Innovus, StarRC, EMIR analysis, ICC2, Voltus

Shell, Perl, Python, Tcl, RedHawk-SC, Asic Physical Design, LVS, current-density violations, UPF, signoff flows, Electromigration, Physical Verification, Static Dynamic IR Drop, ECO recommendations, EMIR analysis, DRC, PG connectivity, STA concepts, Multi-Voltage Multi-Power-Domain designs, CPF, signoff closure, EMIR debugging

FPGA Design, Perl, Verilog, Python, systemverilog, Synthesis Checks, Digital Design, Custom IP Development