Soc, Scripting Languages, LVS, power plan, UPF, Place Route, Tweaker, PrimeClosure, Cadence Tools, STA flow methodology, ESD analysis, Floor plan, primetime, Tempus, IP level Synthesis, analog digital interface, formal verification, ERC, IO ring, DRC

redhawk , Ecos, Perl, Fc, Tcl, Sta, CPU Domain, Pt, Tempus, Physical Design, Innovus, Genus, Voltas

Routing, Placement, Synthesis, GDSII, IR Drop Analysis, SoC Physical Design, Signal Integrity Closure, ICC Innovus, floorplanning, CTS, Power Physical Verification, Sta

Tcl Scripting, RTL synthesis, Conformal, Synopsys Fusion Compiler, LEC, VCLP, UPF, Cadence Genus