DDR, Pcie, Ethernet, Verification plan and coverage model, FPGA verification, ARM RISC-V based compute Sub-Systems, Security Sub-system, SoC IP verification architecture, UCIe, Low-power performance emulation, NoC Debug, Emulation based acceleration with Palladium Zebu or Veloce, UVM-based verification environments, UVM SystemVerilog Assertions, AI-assisted verification flows