System Verilog, Asic verification, SoC Verification, digital design verification, Uvm, GIT version control

.NET, snowflake , Logging, SQL Server, React, Dashboarding, metrics, Python, distributed tracing, Google Vertex AI Agent Builder, AI-powered coding assistants, observability

Selenium, Python, Agile Software Testing Methodologies, Test Design Techniques, Playwright, AI-assisted agent-driven development tools, Regulatory Compliance, Risk-based Testing, Test Automation Frameworks

Scripting Languages, Selenium, Python, Risk-based testing, Playwright, ISTQB Foundation certification, Regulatory Compliance, Agile-aligned test strategies, AI-assisted agent-driven development tools, Test automation frameworks, Test design techniques, Agile software testing methodologies, Data AI clinical solutions

System Verilog, Functional Coverage, Digital-Analog Co-Simulations, Mixed Signal Verification Methodology, Uvm, PLL Verification, Digital Design, Low Power RTL Verification

Debugging skills, AI ML techniques, Uvm, systemverilog, Coverage-driven verification

DDR, Pcie, Perl, Ethernet, Python, Design Verification, Uvm, emulation environments, RTL Verilog, HBM, SoC IP, high-speed protocols, AI ML SoCs

Ovm, Spi, Shell, Pcie, Verilog, I2c, Python, Usb, Can, Perl, Ethernet, Tcl, ARM Protocols, IP Verification, Uvm, GLS, Mipi, Emulation, Test bench model VIP development, dsi, LPDDR, CSI, SoC Verification, SV, AMs, LEC, Functional coverage, Axi, APB, AHB

System Verilog, chip design flow, Specman, ASIC standard interfaces, constrained-random verification environments, verification techniques, design verification methodologies, hardware verification languages, memory system architecture