Pcie, Perl, Vcs, Verilog, Ethernet, I2c, Spi, System Verilog, MTI, NC, Uvm

Tcl, System Verilog, Perl, Ethernet Subsystem SoC verification, Uvm, Synopsys, BFMs, Constrained random verification, Scoreboards, Code functional coverage, Cadence, Gate-level SDF simulations, Monitors, Block system level verification plans and tests, Checkers, Ethernet MAC PCS and SerDes SoC verification

AI ML techniques, Uvm, systemverilog, Coverage-driven verification

C, C++, Verilog, Tcl, Python, Xml, Perl, systemverilog, formal verification, Assertions, UVM methodology, Synopsys, Verification simulation, Silicon process technologies, Coverage-driven verification, Cadence, VHDL, Formal debug, Constrained-random testing, Regression management, SoC verification environments

data engineering , bedrock , Python, Java, Tensorflow, AWS, Pytorch, Azure, Computer Vision, Scikit-learn, data pipeline development, Azure OpenAI, Langchain, Cline Aider, MCP, DevOps practices, Crew AI

software design patterns , optimization models , computational complexity , Java, Pyspark, Sql, Python, C#, Distributed Computing, Advanced Data Structures, C++, CPLEX, Go, mathematical programming, Gurobi, Object-oriented programming, Custom heuristics, Google OR-Tools, Network Flow, Algorithmic design

RTL, CPU DV, Uvm, verification strategy, microarchitecture verification, high-performance out-of-order CPU verification, AI-assisted verification workflows, CVM, Isa, testbench development, regressions, complex debug, Coverage

Device Drivers, Linux kernel, Uart, Automated Testing, Programming, Spi, Freertos, I2c, Python, PHY MAC layer drivers for WiFi for Linux, board bring-up in Linux, Wireless firmware, memory mapped devices in Linux and RTOS environments

DVCS e.g. Git, Sql, C, Xpath, Gcc, HTML, Xslt, Dom, Linux, Xml, Python, Javascript, LLVM, Uvm, SGE or other DRMS, systemverilog, Assembly languages, SVA