Matlab, Worst case identification, Monte Carlo analysis, Physical layout management, AMs, Analog Circuit Design, Spectre, Cadence tool set, Top level simulation, Simplis, Post layout parasitic extraction, Schematic generation and simulation, Top level verification, Knowledge of device physics and process technologies, Block level modelling, Simulation data analysis, IC transistor level implementation, IC system partitioning and architectural tradeoff analysis, Power IC design, Signal grounding and routing tradeoffs, Die area optimization

cadence spectre , mosfet , Synopsys tool suites, aging effects, small-signal modeling, jitter, BJT device physics, crosstalk, Verilog-AMS, Mentor Graphics, Cadence Virtuoso, Verilog-A, thermal noise