logic bist , boundary scan , Scan Insertion, Multi-voltage power-gated designs, Transition Path Delay, MBIST, Synopsys TestMAX, Scan compression, Siemens Mentor Tessent, DFT architecture, ATPG, Cadence Modus, IEEE 1149.1, Hierarchical DFT, Stuck-at

Test Planning, Vcs, Jtag, Shell, Perl, Python, Tcl, GLS Signoff, Fusion Compiler, Xcelium, Silicon Bring-up, MBIST, Scan Insertion, Tessent, ATPG, Conformal Formality, Genus, DFT RTL Design Integration, Debug Diagnosis, LBIST, IJTAG, DFT Architecture