Jtag, IEEE 1500 Standard, SSN, Mentor Synopsys test generation tools, MBIST, BSCAN, scan compression, ATPG, Tessent shell flow, Sta, DFT design, yield learning, DFT instruments insertion, logic diagnosis, Synthesis, test pattern translation, LBIST, back-end implementation flows, occ

logic bist , Usb, Perl, Pcie, Shell scripting, Static Timing Analysis, Python, Tcl, Memory BIST, Mentor, Cadence, IEEE 1149.1 JTAG, IEEE 1500, Analog Mixed-Signal test structures, DFT architecture, ATPG, EDA Tools, IEEE 1687 IJTAG, Siemens, Synopsys

Gate level simulations, Synthesis, Timing Constraints, Logicbist insertion, ATPG, Digital RTL coding, Siemens, Cadence, Mentor, Synopsys, TetraMax