THE ROLE:

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's high-speed SERDES IP, ensuring robust functionality, performance, and reliability across a wide range of operating conditions. The successful candidate will play a key role in developing and validating cutting-edge wireline communication technologies used in AMD products, driving design quality and helping achieve first-silicon success with zero critical bugs in the final design.

THE PERSON:

The ideal candidate should possess a strong background in high-speed analog and mixed-signal circuit design, coupled with a deep understanding of SERDES architectures and wireline communication systems. They should be technically strong, highly collaborative, and comfortable working in a global development environment. The candidate must be able to lead technical discussions, participate in design and architecture reviews, present complex concepts to engineering teams worldwide, and provide mentorship to junior engineers when required.

KEY RESPONSIBILITIES:

Design and develop wireline transceiver building blocks, including PLLs, clock distribution networks, receiver front-end circuits, transmitter front-end circuits, serializers, deserializers, and other high-speed analog functions.
Perform circuit simulations and analysis to ensure designs meet performance, power, area, and reliability targets.
Conduct peer reviews of circuit designs, verification methodologies, simulation results, and technical documentation to ensure design quality.
Collaborate closely with architecture, layout, verification, and system teams throughout the design cycle.
Support silicon bring-up and debug activities, working with validation teams to correlate simulation results with silicon performance.
Drive root-cause analysis and implement design improvements based on silicon characterization and validation findings.
Contribute to design methodologies and best practices to enhance overall team productivity and design robustness.

PREFERRED EXPERIENCE:

Extensive experience in high-speed analog and mixed-signal circuit design, particularly with blocks such as ADCs, PLLs, clock distribution circuits, receiver front-end circuits, transmitter front-end circuits, serializers, and deserializers.
Strong understanding of SERDES architectures, signal integrity, jitter analysis, equalization techniques, and high-speed interface design.
Experience designing and delivering products in advanced semiconductor process technologies, including 7nm FinFET and below.
Hands-on experience with industry-standard analog design, simulation, and verification tools.
Proven track record of successfully bringing complex analog or mixed-signal designs from concept through silicon validation and production.
Ability to work effectively in cross-functional and geographically distributed engineering teams.

ACADEMIC CREDENTIALS:

Bachelor's, Master's, or PhD degree in Electronic Engineering, Electrical Engineering, Microelectronics, or a related discipline.
Strong academic foundation in analog circuit design, semiconductor devices, communication systems, and integrated circuit design principles.

Principal Analog Mixed Signal Circuit Design Engineer, SERDES