Uart, Spi, FPGA Design, Hdl Languages, Pcie, Verilog, I2c, System Verilog, Ethernet based protocols, Unix system, Otn, Uvm, Microsemi FPGAs, quartus, VHDL, Vivado, VMM, AXI memory controllers, Libero

System Verilog, Gate Level Simulations, Building test benches from scratch, ASIC verification using UVM

boundary scan , Vcs, Perl, System Verilog, Python, Tcl, Memory BIST, primetime, Logic Equivalency checking, P1687, TetraMax, Gate level simulation debugging, Scan and BIST architectures, ATE patterns, Tessent, JTAG protocols, ATPG, EDA Tools, TestMax

C, Verilog, Gdb, System Verilog, Python, Tcl, Zebu, Veloce, Palladium, waveform debuggers