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Showing 4 jobs
Skills:
Tcp, Ipv4, Perl, Pcie, Ethernet, System Verilog, Python, Gate Level Simulations, RDMA, vc formal, System Verilog constraints structures and classes, Palladium, Uvm, Emulation, Zebu, Veloce, iev, HAPS, formal verification
Skills:
Perl, Python, System Verilog, Building test benches from scratch, Zebu, Veloce, ASIC verification using UVM, Palladium, HAPS
Skills:
System Verilog, Gate Level Simulations, Building test benches, ASIC verification using UVM, formal verification
Skills:
C, Verilog, Gdb, System Verilog, Python, Tcl, Veloce, Zebu, Palladium, waveform debuggers
