Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

Qualcomm is hiring strong DV engineers to verify high performance and low power CPUs in Bangalore. Please forward your profiles if you meet the requirement.

Roles and Responsibilities

Responsible for power management verification includes Boot, Reset, clock gating, power gating, Voltage/frequency management, limit management and throttling.
Work closely with design/verification teams within CPU to develop comprehensive test plan.
Use simulation and formal verification methodologies to execute test plans. Write checkers, assertions and develop stimulus.
Verify power intent through use of methodologies like UPF.
Work closely with system architects, software teams and Soc team to validate system use cases.
Work closely with emulation team to enable verification on emulators and FPGA platforms.
Debug and triage failures in simulation, emulation and/or Silicon.

Minimum Qualifications

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

BE/BTech degree in CS/EE with 12+ years experience.

Experience in power management verification.
Implementation of assembly and C language embedded firmware.
Experience in C/C++, scripting languages, Verilog/system Verilog.
Strong understanding of power management features in CPUs and CPU based Socs.
Experience in verification of power management features such as clock gating, power gating, UPF, DVFS/DCVS, reliability, throttling etc.

Preferred Requirements

Good Understanding of CPU architectures and CPU micro-architectures.
In-depth knowledge of digital logic design, micro-processor, debug feature, and DFT architecture and microarchitecture
Experience with advanced verification techniques such as formal and assertions is a plus
Knowledge and verification experience in DFT and structural debug concepts and methodologies: JTAG, IEEE1500, MBIST, scan dump, memory dump is a plus

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CPU Design Sr Staff Verification Engineer