Cadence VLE, Mentor Graphic Calibre DRC, Physical verification of custom layout, Analog Layout fundamentals

power optimization , FPGA Design, floorplanning, Place And Route, Timing Analysis, DRC/LVS Checks, Signal Integrity, Physical Verification, RTL Synthesis, Circuit Layout

device physics matching techniques, OPAMP circuits, Oscillators, Cadence Layout tools Virtuoso, Temperature Sensor, ESD Latchup mitigation techniques, VXL compliance, Mentor Graphics verification tools Calibre, analog and mixed-signal layout techniques, Custom Analog Layout, DACs, Bandgaps, Bias Circuits, ADCs, circuit parasitic extraction reduction, LDOs, Physical Verification LVS DRC ERC ANT with Calibre

layout techniques for analog and mixed-signal circuits, Cadence Virtuoso Layout Editor VLE VXL, Mentor Graphics Calibre DRC LVS

Mentor Graphic Calibre DRC, Cadence VLE, TSMC 3nm, Design and development of critical analog mixed-signal custom digital block, LVS, Full chip level integration support