Cadence VLE, Mentor Graphic Calibre DRC, Analog Layout fundamentals, Physical verification of custom layout

PEX, analog mixed-signal IC design flows, deep-submicron advanced-node technologies, CMOS analog layout techniques, LVS, custom analog IC layout, layout methodology automation, parasitics, ERC, DRC, layout-dependent effects, Cadence Virtuoso, device physics

Dac, ADC, Pll, Calibre, Analog Layout, DRC, virtuoso, LVS, Bandgap

Requirements Management, Design Verification Validation, Electrical Electronics Biomedical Engineering degree, Electrical Safety, Power electronics power management, PCB design review, Design Controls, Altium OrCAD or equivalent, EMC EMI, Schematics and PCB layout, Analog and digital electronics, DFMEA Risk Management, Microcontrollers embedded hardware, HW SW integration, Sensors and instrumentation, Knowledge of IEC 60601 ISO 14971 ISO 13485 and FDA requirements, Hardware testing and debugging

Verilog, Matlab, analog mixed-signal behavioral model development, AFS, high-resolution low-power ADC architectures, IC design CAD tools, lab instruments, design optimization verification, Spectre, analog CMOS integrated circuit design, IC technology and layout, Spice, transistor-level CMOS analog and mixed-signal blocks, VHDL, mixed-mode simulation tools, Siemens Symphony, Cadence Virtuoso, schematic entry

Usb, Dac, Sata, adc, Layout Design