Perl, Python, Tcl, Assertions SVA, Constrained-random verification, Uvm, Functional coverage, systemverilog

Perl, Python, Tcl, Assertions SVA, Constrained-random verification, Uvm, Functional coverage, systemverilog

Tcl, Python, Perl, Assertions SVA, high-speed PHY IPs, Functional coverage, Uvm, CI CD verification flows, systemverilog, AI-assisted verification productivity, Constrained-random verification, verification automation frameworks

Verilog, System Verilog, assertion and coverage-driven verification, Synopsys VCS, Cadence IES, formal property checking tools, verification management tools, Uvm, SVA

Verilog, System Verilog, SVA, Synopsys VCS, assertion and coverage-driven verification, Uvm, formal property checking tools, Cadence IES