System Verilog, Asic verification, SoC Verification, digital design verification, Uvm, GIT version control

rtl verification , simvision , Gen5., Pcie, PCI Express, Design Verification, design verification testing, DV, systemverilog, Uvm, SVA, TLP, DLLP, LTSSM, Verification IP, vip, Functional Coverage, Assertions, Axi, Vlsi, Semiconductor, Verdi, DVE, Gen3, Gen4

Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, Post-silicon debugging, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming

performance verification of ASICs, assertion-based verification, Uvm, formal tools, ASIC standard interfaces, systemverilog, Design Verification, memory system architecture, verification components

Ovm, Spi, Shell, Pcie, Verilog, I2c, Python, Usb, Can, Perl, Ethernet, Tcl, ARM Protocols, IP Verification, Uvm, GLS, Mipi, Emulation, Test bench model VIP development, dsi, LPDDR, CSI, SoC Verification, SV, AMs, LEC, Functional coverage, Axi, APB, AHB

System Verilog, Building test benches from scratch, ASIC verification using UVM

Perl, Shell scripting, Python, Low Power Verification UPF CPF, AMBA AXI AHB APB, USB 2.0 3.x, ARM-based SoCs, SystemVerilog UVM

Jtag, Perl, Verilog, Python, System Verilog, Tcl, Mentor Questa, Cadence Xcelium, JasperGold, Uvm, Synopsys VCS, LP6, LP5, APB, CRI, DDR5, DDR4, IJTAG

DDR, Pcie, Verilog, Ethernet, Python, Cadence Incisive, UCIe, Uvm, Synopsys VCS, formal verification, VHDL, Modelsim