Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, AMBA, Test Bench, transaction level modeling, AXI4

Shell, Perl, Python, Tcl, Cadence Xcelium, Mentor QuestaSim, PCI Express, Uvm, systemverilog, Synopsys VCS, Assertion-Based Verification, Constrained Random Verification, Functional Verification

simvision , Verilog, FineSim, Analog Custom Virtuoso, Xcelium, WaveView, systemverilog, debug environments, AMS verification Tools, Hspice, Cadence DiscoveryAMS, Digital Simulation Tools, Spice, PrimeSim, Synopsys XA

Perl, Python, Tcl, Functional Coverage, Uvm, SVA, systemverilog, ASIC SoC Subsystem IP verification

Verilog, Ovm, DFI protocol, LPDDR4, DDR PHY verification, Uvm, JEDEC standards, systemverilog, LPDDR5

Usb, DDR, Perl, Pcie, Ethernet, Python, Tcl, Uvm, coverage-driven verification, systemverilog, digital design RTL understanding, AMBA, MIPI, SVA

Perl, Python, System Verilog, verification flows, formal verification, verification methodologies, coverage metrics, Profiling Tools, Uvm, constraint random verification

Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Design Verification, Debugging RTL Verilog designs