static timing analysis, industry-standard EDA tools for physical design and verification, Synthesis, RTL-to-GDS workflows, multi-power domain analysis, Place And Route, low-power design techniques, Clock Tree Synthesis

clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, Power Mesh, PNR Floor Plan, Timing Signoff

ECO Change Order, power integrity , Routing, Timing Optimization, EMIR Analysis, LVS, Cadence Innovus, Physical Verification, floorplanning, Physical Design, Crosstalk Analysis, Signal Integrity Closure, DRC

Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology

power optimization , Scripting, Perl, Python, Tcl, Mentor, Cadence, Physical design flows, EDA Tools, Synopsys, Signal Integrity, Timing Analysis

Unix, Perl, Linux, Shell scripting, Python, Tcl, Place Route Cadence Innovus, Physical Verification Calibre DRC LVS, IR EM Cadence Voltus RedHawk, STA Cadence Tempus