PCIe Formal Verification Engineer, PCI Express, formal verification, FPV, SVA, SystemVerilog Assertions, Questa Formal

Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, AMBA, Test Bench, transaction level modeling, AXI4

Switch, Pcie, Virtualization, Verification tools for simulation and debug, UFS, XUSB, High Speed IO verification, 1G Ethernet MAC, Uvm, Security, Sensor processing, Memory controller verification, Axi, Interconnect verification, APB, VMM, Safety, CPU verification, formal verification

Shell, Perl, Python, Tcl, Cadence Xcelium, Mentor QuestaSim, PCI Express, Uvm, systemverilog, Synopsys VCS, Assertion-Based Verification, Constrained Random Verification, Functional Verification

SoC Verification, formal verification techniques and tools, model checking, equivalence checking

simvision , Verilog, FineSim, Analog Custom Virtuoso, Xcelium, WaveView, systemverilog, debug environments, AMS verification Tools, Hspice, Cadence DiscoveryAMS, Digital Simulation Tools, Spice, PrimeSim, Synopsys XA

Perl, Python, Tcl, Functional Coverage, Uvm, SVA, systemverilog, ASIC SoC Subsystem IP verification

Verilog, Ovm, DFI protocol, LPDDR4, DDR PHY verification, Uvm, JEDEC standards, systemverilog, LPDDR5