boundary scan , Vcs, Perl, Python, Tcl, sdf debugging, Scan Insertion, Jtag protocols, memory BIST, TetraMax, Verilog design, p1687, p1500, Gate level simulation, ATPG, EDA Tools, Timing Closure, BIST architectures, Test static timing analysis, Tessent tool sets, timing based simulations, TestMax

automation, Scripting, Shell, Tcl, Python, MBIST, Test Access Mechanisms, systemverilog, ATPG, gate-level simulations, DFT architecture, Tessent, Scan, ATE patterns, testbench development, Debug, Simulation