Logic Design, Perl, Python, DFT Engineering, SV, coverage metrics, Profiling Tools, Uvm, X prop, Post Silicon Testing, constrained random testing, Architecture Verification

scripting skills in Perl, tessent DFT, DFT architecture definition, HDLs, Genus, Scan, MBIST, Cadence digital implementation tools, Tempus, JTAG boundary scan, ATPG flow implementation

Perl, Python, LINT, Sta, Synthesis, DFT timing, DFT EDA Tool Tessent, LEC, Low Power designs

Full Scan Compression, JTAG Boundary Scan, ATPG pattern generation, Scan chains, Fault Simulation

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools

logic bist , Makefile, Windows, Perl, Linux, Verilog, Ruby, System Verilog, DFT verification, Memory BIST, UVM testbenches, Scan ATPG

Test Execution, Perl, Python, SV, DFT Engineering, Pre-Silicon Simulation, Uvm, Verification methodologies, Post Silicon Testing, High Speed IOs, Debug, Automation flow development

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, simulation profile efficiency improvement, debugging firmware and RTL code using simulation tools, UVM based verification frameworks, TLM