Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, AMBA, Test Bench, transaction level modeling, AXI4

C, Pcie, Perl, Python, Tcl, UFS, HSIO PHY Controllers, Skill, Open Verification Methodology, USB2, systemverilog, MIPI, USB3, Universal Verification Methodology

Verilog, Ovm, DFI protocol, LPDDR4, DDR PHY verification, Uvm, JEDEC standards, systemverilog, LPDDR5

Switch, Pcie, Virtualization, Verification tools for simulation and debug, UFS, XUSB, High Speed IO verification, 1G Ethernet MAC, Uvm, Security, Sensor processing, Memory controller verification, Axi, Interconnect verification, APB, VMM, Safety, CPU verification, formal verification

rtl verification , Automation, Verilog, Python, FineSim, AMS verification, Transistor-level verification, Mixed-signal coverage analysis, AI-assisted solutions, Circuit Analysis, Uvm, Functional code assertion, systemverilog, CMOS design fundamentals, Hspice, Mixed-signal architectures, Semiconductor device behavior, Spice, EDA workflow optimization

Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Shell, Perl, Python, Tcl, Cadence Xcelium, Mentor QuestaSim, PCI Express, Uvm, systemverilog, Synopsys VCS, Assertion-Based Verification, Constrained Random Verification, Functional Verification