Gerrit, Pdcp, Networking, Rlc, Qos, Ip Routing, Python, Java, Bash, Jenkins, Mac, Git, Linux, Lte, switching, latency, QoE, CI CD, system-level verification, traffic generation, throughput, Resource Utilization, 5G New Radio NR, PHY, Channel emulators, Ip, RAN architecture, UE simulators, Performance Analysis

cache coherency , Perl, Python, Cache, ACE protocols, C-based testbench development, systemverilog, AMBA, Axi, ISA verification, Memory Subsystems, ARM processor architecture

System Verilog, Verilog RTL coding, ASIC design methodologies, constraint random-driven verification, Uvm, assertion-based verification, RAL, GLS Gate-Level Simulation

Usb, Mac, Perl, Pcie, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB

Usb, Can, Lin, Flexray, Pcie, Verilog, Ethernet, System Verilog, Functional Coverage Development, UVM Testbench Coding, IP SOC Verification, Design Verification Failure Debugging, Axi, Coverage Closure, APB, Assertion Checker Development, Testcase Planning Development, CXL, AHB, Digital Design

Usb, Fpga, Pcie, Perl, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, test bench infrastructure, FPGA and emulation platforms, AMBA, transaction level modeling, AXI4

Perl, Verilog, Gdb, Python, SV-UVM, Verification methodologies, Indago, e-specman, Cadence