Test Plans, industry standard protocols, Asic verification, Gate level simulations, Power aware simulations, constraint-random verification, SV UVM, test bench architecture

C, Perl, Verilog, Shell scripting, Python, Tcl, UVM assertions, systemverilog, SVA

Pcie, Perl, Python, System Verilog, Tcl, CHI, SMMU, assertion-based verification, Uvm, Coresight, Axi, coverage-driven testing, CXL, SVA

cache coherency , Vcs, Perl, Python, Tcl, CHI, Ace, Xcelium, AMBA protocols, Uvm, NoC Integration, systemverilog, Performance Validation, Axi, Questa

Verilog, VHDL, formal verification, JasperGold, VC Formal, Object-oriented Programming, Formal Abstraction Techniques, systemverilog